The function generators in 7 series FPGAs are implemented as six-input look-up tables (LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The function generators can implement:
- Any arbitrarily defined six-input Boolean function
- Two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs
- Two arbitrarily defined Boolean functions of 3 and 2 inputs or less
A six-input function uses:
- A1-A6 inputs
- O6 output
Two five-input or less functions use:
- A1–A5 inputs
- A6 driven High
- O5 and O6 outputs
The propagation delay through a LUT is independent of the function implemented. Signals from the function generators can:
- Exit the slice (through A, B, C, D output for O6 or AMUX, BMUX, CMUX, DMUX output for O5)
- Enter the XOR dedicated gate from an O6 output
- Enter the carry-logic chain from an O5 output
- Enter the select line of the carry-logic multiplexer from O6 output
- Feed the D input of the storage element
- Go to F7AMUX/F7BMUX wide multiplexers from O6 output
In addition to the basic LUTs, slices contain three multiplexers (F7AMUX, F7BMUX, and F8MUX). These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice.
- F7AMUX: Used to generate seven input functions from LUTs A and B
- F7BMUX: Used to generate seven input functions from LUTs C and D
- F8MUX: Used to combine all LUTs to generate eight input functions.
Functions with more than eight inputs can be implemented using multiple slices. There are no direct connections between slices to form function generators greater than eight inputs within a CLB.
Address Collision
Address collision in synchronous multi-port RAM can produce non-deterministic result at the synchronously capture read output. As shown in Figure 1, distributed RAM read is asynchronous in a CLB. To make sure the output is deterministic, read and write operation should happen in different clock cycle. If the read addresses are registered at system level so that both read and write operation are synchronous, our timing tools like Vivado impose the needed timing constrains to make the output is deterministic.