Interconnect is the programmable network of signal pathways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DSP slices, and block RAM. Interconnect, also called routing, is segmented for optimal connectivity. The AMD placement and routing tools exploit the rich interconnect array to deliver optimal system performance and the fastest compile times.
The 7 series CLBs are arranged in a regular array inside the FPGA. Each connects to a switch matrix for access to the general-routing resources, which run vertically and horizontally between the CLB rows and columns. A similar switch matrix connects other resources, such as the DSP slices and block RAM resources.
Most of the interconnect features are transparent to FPGA designers. Knowledge of the interconnect details can be used to guide design techniques but is not necessary for efficient FPGA design. Only selected types of interconnect are under user control. These include the clock routing resources, which are selected by using clock buffers and discussed in more detail in 7 Series FPGAs Clocking Resources User Guide (UG472). Two global control signals, GSR and GTS, are selected by using the STARTUPE2 primitive.