Interconnect delays vary according to the specific implementation and loading in a design. The type of interconnect, distance required to travel in the device, and number of switch matrices to traverse factor into the total delay. Most timing issues are addressed by examining the block delays and determining the impact of using fewer levels or faster paths. If interconnect delays seem too long, increase implementation effort levels or iterations to improve performance along with making sure that the required timing is in the constraints file.
Nets with critical timing or that are heavily loaded can often be improved by replicating the source of the net. The dual 5-input LUT configuration of the slice simplifies the replication of logic in the same slice, which minimizes any additional loads on the inputs to the source function. Replicating logic in multiple slices gives the software more flexibility to place the sources independently.
Floorplanning is the process of specifying user-placement constraints. Floorplanning can be done either before or after automatic place and route, but automatic place and route is always recommended first before specifying user floorplanning. The AMD implementation tool provides a graphical view of placement. It helps the designer choose between RTL coding and synthesis and implementation, with extensive design exploration and analysis features.