In addition to the general-purpose interconnect, 7 series FPGAs have two global logic control signals, as described in the following table.
| Global Control Input | Description |
|---|---|
| GSR | Global Set/Reset: When High, asynchronously places all registers and flip-flops in their initial state. |
| GTS | Global 3-State: When High, asynchronously forces all I/O pins to a high-impedance state (High-Z, 3-state). |
If a common initialization signal is needed for every flip-flop in the design, use the GSR control in a design instead of a separate routed global reset signal to make CLB inputs available, which results in a smaller more efficient design. The GSR signal must always re-initialize every flip-flop. Using GSR and GTS does not use any general-purpose routing resources. The GSR signal is asserted automatically during the FPGA configuration process, guaranteeing that the FPGA starts up in a known state. At configuration, because flip-flops are enabled by the configuration clock and then clocked by a user clock, it is recommended to enable key flip-flops or key clock signals on the user clock after configuration.