General Timing Parameters - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID: UG474
Release Date: 2025-04-01
Revision: 1.9 English

The following table shows the general slice timing parameters for a majority of the paths in Figure 1.

Table 1. General Slice Timing Parameters
Parameter	Function	Description
Combinatorial Delays
T_ILO ⁽¹⁾	A/B/C/D inputs to A/B/C/D outputs	Propagation delay from the A/B/C/D LUT inputs of the slice, through the look-up tables (LUTs), to the A/B/C/D outputs of the slice.
T_ITO	A/B/C/D inputs through transparent latch to AQ/BQ/CQ/DQ outputs	Propagation delay from the A/B/C/D LUT inputs of the slice, through the LUTs to the AQ/BQ/CQ/DQ outputs of the slice sequential elements (configured as a latch).
Sequential Delays
T_CKO	FF Clock (CLK) to AQ/BQ/CQ/DQ outputs	Time after the clock that data is stable at the AQ/BQ/CQ/DQ outputs of the slice sequential elements (configured as a flip-flop).
T_CKLO	Latch Clock (CLK) to AQ/BQ/CQ/DQ outputs	Time after the clock that data is stable at the AQ/BQ/CQ/DQ outputs of the slice sequential elements (configured as a latch).
T_SHCKO	FF Clock (CLK) to AMUX/BMUX/CMUX/DMUX outputs	Time after the clock that data is stable at the AMUX/BMUX/CMUX/DMUX outputs (through the slice flip-flops).
Setup and Hold Times for Slice Sequential Elements⁽²⁾
T_AS/T_AH	A/B/C/D inputs	Time before/after the CLK that data from the A/B/C/D LUT inputs of the slice must be stable.
T_DICK/T_CKDI	AX/BX/CX/DX inputs	Time before/after the CLK that data from the AX/BX/CX/DX inputs of the slice must be stable.
T_CECK/T_CKCE	CE input	Time before/after the CLK that the CE input of the slice must be stable.
T_SRCK/T_CKSR	SR input	Time before/after the CLK that the SR (Set/Reset) input of the slice must be stable.
Set/Reset
T_RPW(T_SRMIN)	SR input	Minimum pulse width for the SR (Set/Reset).
T_RQ	SR input	Propagation delay for an asynchronous Set/Reset of the slice sequential elements.
Miscellaneous
T_CEO	CE input	Propagation delay from CE enable to latch output at AQ/BQ/CQ/DQ outputs.
F_TOG	CLK input	Toggle Frequency – Maximum frequency that a slice flip-flop can be clocked. For export control.
This parameter includes a LUT configured as two five-input functions. T_XXCK = Setup Time (before clock edge), and TCKXX = Hold Time (after clock edge).