The following figure illustrates the general timing characteristics of a 7 series FPGA slice.
Figure 1. General Slice Timing Characteristics
- At time TCECK before clock event (1), the clock-enable signal becomes valid-High at the CE input of the slice register.
- At time TDICK before clock event (1), data from either AX, BX, CX, or DX inputs become valid-High at the D input of the slice register and is reflected on either the AQ, BQ, CQ, or DQ pin at time TCKO after clock event (1).
- At time TSRCK before clock event (3), the SR signal (configured as synchronous reset) becomes valid-High, resetting the slice register. This is reflected on the AQ, BQ, CQ, or DQ pin at time TCKO after clock event (3).