This chapter provides a detailed view of the 7 series FPGAs CLB architecture. These details can be useful for design optimization and verification, but are not necessary for initiating a design. This chapter includes:
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Overview of slice locations and features within the CLB
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Complete details of SLICEM and SLICEL
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Description of the logical function generators
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Description and controls for the latches and flip-flops
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SLICEM ability to use LUTs as writable memory
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SLICEM ability to use LUTs as shift registers
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Dedicated gates for combining LUTs into wide functions
Dedicated gates and cascading to implement efficient arithmetic functions.