There are several primitives for the CLB storage elements, including both flip-flops and latches, with different combinations of control signals available. The FDRE primitive is shown in the following figure for an example. For more information on the flip-flop and latch primitives, see Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953).
Figure 1. FDRE Primitive
