Enable – WE/WED - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The enable pin affects the write functionality of the port. An inactive write enable prevents any writing to memory cells. An active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs.