The following table shows the timing parameters for the distributed RAM in SLICEM for a majority of the paths in Figure 1.
| Parameter | Function | Description |
|---|---|---|
| Sequential Delays for a Slice LUT Configured as RAM (Distributed RAM) | ||
| TSHCKO | CLK to A/B/C/D outputs | Time after the CLK of a write operation that the data written to the distributed RAM is stable on the A/B/C/D outputs of the slice. |
| TSHCKO (TSHCKO_1) | CLK to AMUX/BMUX/CMUX/DMUX outputs | Time after the CLK of a write operation that the data written to the distributed RAM is stable on the AMUX/BMUX/CMUX/DMUX outputs of the slice. |
| Setup and Hold Times for a Slice LUT Configured as RAM (Distributed RAM)(1) | ||
|
TDS/TDH (TDS_LRAM/TDH_LRAM) |
AI/BI/CI/DI configured as data inputs (DI1)(2) | Time before/after the clock that data must be stable at the AI/BI/CI/DI inputs of the slice (configured as RAM). |
| TAS/TAH(TAS_LRAM/TAH_LRAM) | A/B/C/D address inputs | Time before/after the clock that address signals must be stable at the A/B/C/D LUT inputs of the slice (configured as RAM). |
| TWS/TWH(TWS_LRAM/TWH_LRAM) | WE input | Time before/after the clock that the write enable signal must be stable at the WE input of the slice (configured as RAM). |
| Clock CLK | ||
| TMPW(TMPW_LRAM) | Minimum clock pulse width for distributed RAM. | |
| TMCP | Minimum clock period to meet address write cycle time. | |
|
||