Distributed RAM Timing Characteristics - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)
Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The timing characteristics of a distributed RAM implemented in a 7 series FPGA slice (LUT configured as RAM) are shown in the following figure.

Figure 1. Slice Distributed RAM Timing Characteristics

Clock Event 1: Write Operation

During a Write operation, the contents of the memory at the address on the ADDR inputs are changed. The data written to this memory location is reflected on the A/B/C/D outputs synchronously.

  • At time TWS before clock event 1, the write-enable signal (WE) becomes valid-High, enabling the RAM for a Write operation.
  • At time TAS before clock event 1, the address (2) becomes valid at the A/B/C/D inputs of the RAM.
  • At time TDS before clock event 1, the DATA becomes valid (1) at the DI input of the RAM and is reflected on the A/B/C/D outputs at time TSHCKO after clock event 1. This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time TSHCKO after clock event 1.

Clock Event 2: Read Operation

All Read operations are asynchronous in distributed RAM. As long as WE is Low, the address bus can be asserted at any time. The contents of the RAM on the address bus are reflected on the A/B/C/D outputs after a delay of length TILO (propagation delay through a LUT). The address (F) is asserted after clock event 2, and the contents of the RAM at address (F) are reflected at the output after a delay of length TILO.