Distributed RAM Summary - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

Here is a summary of distributed RAM features:

  • Single-port and dual-port modes are available in SLICEMs
  • A write operation requires one clock edge
  • Read operations are asynchronous (Q output)
  • The data input has a setup-to-clock timing specification