As noted in the 7 Series FPGAs Data Sheet: Overview (DS180), some of the Virtex 7 devices use stacked silicon interconnect (SSI) technology. These devices provide a unique additional type of interconnect resource called a super long line or SLL. These special routing resources can be treated like other interconnect resources as they are abundant (more than 10,000) and fast (about 1 ns). The SLL provides a connection between super logic regions (SLRs), as shown in Figure 1. Combining multiple SLRs effectively increases the height of the ASMBL™ architecture columns and increases the overall capacity of the device. The software can be allowed to take best advantage of this configuration, or users can apply floorplanning to control placement within and between SLRs. Carry logic cascading is limited to within an SLR and does not continue through the SLL connections. The same is true of other types of cascading including block RAM, DSP, and DCI. Boundaries are visible in floorplanning tools and reported in timing reports. The number of SLRs per Virtex 7 device is listed in the 7 series FPGAs Overview.
Designs targeting devices using SSI technology only require one STARTUPE2 instantiation. One source for GSR and GTS signals propagates across the SLR boundaries to all elements of the device.
Optimization for devices using SSI technology can start with the same techniques as for any standard device, including using proper design techniques, timing constraints or options to automatically find the best implementation. Floorplanning for these devices can use the same graphical tools.
For more information on devices using SSI technology, see the following: