These guidelines are provided as a quick checklist of design suggestions for effective use of the 7 series CLBs:
- Resource Utilization
- Use generic HDL code and allow the synthesis and mapping tools to choose the specific FPGA CLB resources.
- Consider instantiation of specific resources only when necessary to meet density or performance requirements.
- Compare the results to an estimated slice count to verify design efficiency.
- If a design is running out of resources in the target device, examine which resource is the limiting factor and consider using alternative resources, such as moving registers to SRLs or distributed RAM, or distributed RAM to block RAM, or carry logic to DSP slices.
- When migrating a design from another architecture, remove resource instantiation and any mapping and floorplanning constraints (refer to 7 Series FPGAs Migration Methodology Guide (UG429)).
Refer to www.amd.com for good HDL coding techniques for FPGAs, such as the XST User Guide for Virtex 6, Spartan 6, and 7 series Devices (UG687).
- Pipelining
- The designer should use sequential design techniques and pipelining to take advantage of abundant flip-flops for performance.
- Control Signals
- Use control signals only as necessary.
- Avoid using a routed global reset signal and minimize use of local resets to maximize opportunity to use FPGA resources.
- Use active-High control signals.
- Avoid having both set and reset on the same flip-flop.
- Avoid control signals on small shift registers and storage arrays to use LUTs instead of flip-flops, to maximize utilization and minimize power.
- Software Options
- To improve performance automatically, use timing constraints and trade off longer implementation runtimes through software options.