The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice. When one flip-flop in a slice has SR or CE enabled, the other flip-flops used in the slice also have SR or CE enabled by the common signal. Only the CLK signal has programmable polarity. Any inverter placed on the clock signal is automatically absorbed. The CE and SR signals are active-High.
These initialization options are available for storage elements:
- SRLOW: Synchronous or asynchronous Reset when CLB SR signal is asserted
- SRHIGH: Synchronous or asynchronous Set when CLB SR signal is asserted
- INIT0: Asynchronous Reset on power-up or global Set/Reset (see Global Controls GSR and GTS)
- INIT1: Asynchronous Set on power-up or global Set/Reset
The SR signal forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH forces a logic High at the storage element output when SR is asserted, while SRLOW forces a logic Low at the storage element output (see the following table).
| SR | SRVAL | Function |
|---|---|---|
| 0 | SRLOW (default) | No Logic Change |
| 1 | SRLOW (default) | 0 |
| 0 | SRHIGH | No Logic Change |
| 1 | SRHIGH | 1 |
SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set individually for each storage element in a slice.
The initial state after configuration or global initial state is defined by separate INIT0 and INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. 7 series devices can set INIT0 and INIT1 independent of SRHIGH and SRLOW.
The configuration options for the set and reset functionality of a register or the four storage elements capable of functioning as a latch are:
- No set or reset
- Synchronous set
- Synchronous reset
- Asynchronous set (preset)
- Asynchronous reset (clear)