Either the rising edge or the falling edge of the clock is used to capture data and toggle the output. The data and clock enable input pins have setup times referenced to the chosen edge of the clock. The clock pin (C) has an inversion option at the slice level. The clock signal can be active at the negative or positive edge of the clock without requiring other logic resources. The default is the positive clock edge. All flip-flops in a slice must use the same clock and same clock polarity.