Carry Logic - Carry Logic - UG474

In addition to function generators, dedicated fast lookahead carry logic is provided to perform fast arithmetic addition and subtraction in a slice. A 7 series FPGA CLB has two separate carry chains, as shown in Figure 1. The carry chains are cascadable to form wider add/subtract logic, as shown in Figure 1.

The carry chain runs upward and has a height of four bits per slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for adding/subtracting the operands with a selected carry bits. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions.

The following figure illustrates the carry chain with associated logic in a slice.

The carry chains use carry lookahead logic along with the function generators. There are 10 independent inputs and 8 independent outputs:

• Inputs
  • S inputs - S0 to S3
    • The “propagate” signals of the carry lookahead logic
    • Sourced from the O6 output of a function generator
• DI inputs - DI1 to DI4
  • The “generate” signals of the carry lookahead logic
  • Sourced from either the O5 output of a function generator
    • To create a multiplier
  • Or the BYPASS input (AX, BX, CX, or DX) of a slice
    • To create an adder/accumulator
• CYINIT
  • CIN of the first bit in a carry chain
    • 0 for add
    • 1 for subtract
    • AX input for the dynamic first carry bit
• CIN
  • Cascade slices to form a longer carry chain
• Outputs
  • O outputs - O0 to O3
    • Contain the sum of the addition/subtraction
• CO outputs - CO0 to CO3
  • Compute the carry out for each bit
  • CO3 is connected to COUT output of a slice to form a longer carry chain by cascading multiple slices

The propagation delay for an adder increases linearly with the number of bits in the operand, as more carry chains are cascaded. The carry chain can be implemented with a storage element or a flip-flop in the same slice.

Carry logic cascading is limited only by the height of the column of slices. Carry logic cannot be cascaded across super logic regions (SLRs) in devices using stacked silicon interconnect (SSI) technology. See Devices Using Stacked Silicon Interconnect (SSI) Technology.