The CARRY4 primitive instantiates the fast carry logic available in each slice. This primitive works with LUTs to build adders and multipliers. The following figure shows the CARRY4 primitive. Synthesis tools generally infer this logic from arithmetic HDL code, automatically connecting this function properly.
Port Signals
Sum Outputs - O[3:0]
The sum outputs provide the final result of the addition/subtraction. They connect to the slice AMUX/BMUX/CMUX/DMUX outputs.
Carry Outputs - CO[3:0]
The carry outputs provide the carry out for each bit. CO[3] is equivalent to COUT. A longer carry chain can be created if CO[3] is connected through COUT to the CI input of another CARRY4 primitive, and dedicated routing connects the carry chain up a column of slices. The carry outputs also optionally connect to the slice AMUX/BMUX/CMUX/DMUX outputs.
Carry In - CI
The carry in input, also called CIN, is used to cascade slices to form longer carry chains.
Data Inputs - DI[3:0]
The data inputs are used as “generate” signals to the carry lookahead logic. The “generate” signals are sourced from LUT outputs.
Select Inputs - S[3:0]
The select inputs are used as “propagate” signals to the carry lookahead logic. The “propagate” signals are sourced from LUT outputs.
Carry Initialize - CYINIT
The carry initialize input is used to select the first bit in a carry chain. The value for this pin is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit).