CLB/Slice Configurations - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)
Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

The following table summarizes the logic resources in one CLB. Each SLICEM LUT can be configured as a look-up table, distributed RAM, or a shift register.

Table 1. Logic Resources in One CLB
Slices LUTs Flip-Flops Arithmetic and Carry Chains Distributed RAM(1) Shift Registers(1)
2 8 16 2 256 bits 128 bits
  1. SLICEM only, SLICEL does not have distributed RAM or shift registers.