CLB Slices - UG474

7 Series FPGAs Configurable Logic Block User Guide (UG474)

Document ID
UG474
Release Date
2025-04-01
Revision
1.9 English

A CLB element contains a pair of slices, and each slice is composed of four 6-input LUTs and eight storage elements.

  • SLICE(0) – slice at the bottom of the CLB and in the left column
  • SLICE(1) – slice at the top of the CLB and in the right column

These two slices do not have direct connections to each other, and each slice is organized as a column. Each slice in a column has an independent carry chain.

The AMD tools designate slices with these definitions:

  • An “X” followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc.
  • A “Y” followed by a number identifies a row of slices. The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom.

The following figure shows four CLBs located in the bottom-left corner of the die.

Figure 1. Row and Column Relationship between CLBs and Slices