CLB Slice Multiplexer Timing Model and Parameters - CLB Slice Multiplexer Timing Model and Parameters - UG474
7 Series FPGAs Configurable Logic Block User Guide (UG474)
Document_ID
UG474
Release_Date
2025-04-01
Revision
1.9 English
Figure 1
and
Figure 2
illustrate the wide multiplexers in a
7 series
FPGA slice.