AMD 7 series FPGAs include three FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The AMD Artix™ 7 family is optimized for lowest cost and absolute power for the highest volume applications. The AMD Virtex™ 7 family is optimized for highest system performance and capacity. The AMD Kintex™ 7 family is an innovative class of FPGAs optimized for the best price-performance. This guide serves as a technical reference describing the 7 series FPGAs configurable logic blocks (CLBs).
Usually, logic synthesis assigns the CLB resources without system designer intervention. It can be advantageous for the designer to understand certain CLB details, including the varying capabilities of the look-up tables (LUTs), the physical direction of the carry propagation, the number and distribution of the available flip-flops, and the availability of the very efficient shift registers. This guide describes these and other features of the CLB in detail.
This 7 series FPGAs Configurable Logic Block User Guide, part of an overall set of documentation on the 7 series FPGAs, is available on the AMD 7 Series documentation website.