Error: axis field mismatch - Error: axis field mismatch - 2026.1 English - UG1864

Vitis Functional Simulation User Guide (UG1864)
Document_ID
UG1864
Release_Date
2026-06-23
Version
2026.1 English

This error occurs if both the port and the varray have axis configurations but specific fields differ (for example, the port expects TLAST-only but the varray has all sidebands enabled):

# Kernel expects: hls::axis<int, 0, 0, 0, 16, false>  (TLAST-only, enable_signals=16)
# User provides:  va.axis()  (all sidebands enabled, enable_signals=57)
arr = va.array(data, dtype=va.int32, axis=va.axis())
result = tlast_only_kernel.run(arr)  # TypeError!

The error message lists each mismatched field:

TypeError: Input port 0 axis config mismatch:
  enable_tkeep: expected False, got True
  enable_tstrb: expected False, got True
...
  arr.set_axis(axis(enable_tkeep=False, enable_tstrb=False))

Fix: Update the axis to match the port:

arr.set_axis(va.axis(enable_tkeep=False, enable_tstrb=False))