Description
Find and replace all references of a clock with references of another existing clock by clock name. Optionally restrict replacement to specified list of blocks.
Syntax
replace(<name>, <other_name>, [<block_names>])
Parameters
| Name | Description |
|---|---|
| <name> | Clock name to find. |
| <other_name> | Clock name to replace with. |
| [<block_names>] | List of block names to restrict replacement scope. Default: All blocks |
Examples
# Replace all references of one clock with another across the entire project
proj = open_project('my_design.pdm')
clock_handler = proj.get_clock_handler()
clock_handler.replace('old_clk', 'new_clk')
# Replace clock references only in specific blocks
clock_handler.replace('old_clk', 'new_clk', ['logic', 'bram'])