QSPI - UG1713

This boot mode is supported onboard and is wired to the XCSU35P U2 bank 0 pins. The master SPI configuration mode supports multiple data bus widths and setups. The master SPI configuration mode can read from standard 1-bit (x1), 2-bit (x2), and 4-bit (x4) SPI flash devices. The SCU35 uses the Master SPI_24 (M[0:2]=100), 24-bit addressing variant of the master SPI configuration mode, which supports QSPI flash devices up to 128 Mb.

See the Master SPI Configuration Mode section of the Spartan UltraScale+ FPGAs Configuration User Guide (UG860) for more information. To boot from QSPI:

1. Store a valid XCSU35P FPGA boot image file in the QSPI.
2. Set boot mode selection header J35 for QSPI as indicated in the "Mode Configuration Option Header J35 Settings" table in Spartan UltraScale+ Device Configuration.
3. Power-cycle the SCU35 board or press the program (PROGRAM_B) pushbutton SW2. SW2 is near the HSIO connector J21 in the figure in Board Component Location.