Power Load Switches - UG1713

The SCU35 board provides load switches on the HSIO, MikroBUS (Click), and Pmod I/O expansion interfaces. The load switches provide output current limiting, reverse current blocking, and thermal shutdown protection. The switches are disabled by default at power on (an internal pull-down resistor on the enable input) and are controlled by signals connected to FPGA I/O pins described in the following table. It is up to the user to control these enable signals in their Vivado design when using the associated I/O expansion interface. Unused I/O expansion interfaces can leave the corresponding load switch(es) disabled.

The detailed FPGA connections for the feature described in this section are documented in the SCU35 evaluation board schematic and XDC file, referenced in Xilinx Design Constraints.