The Xilinx design constraints (XDC) file template for the board provides for designs targeting the evaluation board. Net names in the constraints listed correlate with net names on the latest evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.
See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.
The FPGA I/O Banks 45 and 46 are powered by the adjustable voltage
VR_VCCO_45_46_ADJ, which can be set to 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V
(default). This allows great flexibility when using Raspberry Pi HAT modules.
Because different HAT modules implement different circuitry, the I/O standards for
banks 45 and 46 must be uniquely defined by each customer design for all I/Os used
in these banks. For example, if a HAT that requires 1.8 V I/Os is used and also the
GPIOs for the LEDs and switches, the I/O standard for all the I/Os used in these
banks must be set to 1.8V.
Important: See the SCU35 board documentation ("Board
Files" check box) for the XDC file.