The board provides a single-width HSIO Standard interface. All HSIO I/O, except for I2C signals, are connected to HPIO bank 47. The I2C signals are on bank 67.
The XCSU35P differential I/O pairs connected to this HSIO interface operate at 1500 Mb/s line rate.
The HSIO power pins are supplied by 1.8 V, 3.3 V, and 5 V. Load switches are provided for overcurrent and reverse current protection and are enabled by the HSIO_1V8_ON, HSIO_3V3_ON, and HSIO_5V0_ON FPGA I/O signals on bank 6. A combined maximum current of 2.0 A may be drawn from the 1.8 V, 3.3 V, and 5 V rails.
Note: The HSIO interface on the board is based on the Opal Kelly SYZYGY® Standard. However, the
SCU35 board does not provide a SmartVIO Controller for VIO voltage configuration as
described in the SYZYGY specification. As a result, all SCU35 HSIO I/Os (VIO) are
limited to 1.8 V.
More information about SYZYGY boards, mechanical specification, etc. can be found at the SYZYGY website.
Important: The XCSU35P FPGA I/Os are not 5V
tolerant. The maximum voltage that can be applied to the XCSU35P FPGA HP I/Os (bank
47) is Vcco + 0.550V. HSIO boards that require VIO greater than 1.8V cannot be used
with the board. Additionally, the FPGA
bank I/O voltage must match the requirements for the I/O standards that have been
assigned to the I/O bank.