A MII Ethernet MAC IP in the XCSU35P FPGA implements a 10/100 Mb/s Ethernet interface. In the following figure, the FPGA (U2) is connected to a TI DP83867IR Ethernet MII PHY (U31) before being routed to an RJ45 Ethernet connector (P1). The MII Ethernet PHY is strapped to PHY address 0x01 and Auto Negotiation is set to Enable. More information on this Ethernet PHY can be found on the TI website.
Figure 1. MII Ethernet
