The DP83867 PHY (U31) is reset by its ENET_RST_B generated by system power good and FPGA I/O signals as shown in the following figure. The SYS_PGOOD signal generated by the MP2002A (U30) and MP2181 (U39) devices (open drain outputs) is wired to the Ethernet PHY reset circuit. The SYS_PGOOD signal is controlled by pushbutton SW2. See Device Reconfiguration PROGRAM_B for more details.
Figure 1. Ethernet PHY Reset Circuit
