The cooling fan connector is shown in the following figure. The can use the FPGA I/O FAN_EN signal (bank 68, pin A9) to autonomously control the fan speed by controlling the pulse width modulation (PWM) signal to the fan. A controlling software application must be created to monitor the XCSU35P FPGA temperature and drive this logic. A FPGA PWM IP is required in the user design.
The board provides a fan controller header J47 to permit control by the Spartan UltraScale+ device. See the Default Jumper and Switch Settings for more details.
Figure 1. 5V Fan Header
