The board provides several clock sources for the XCSU35P U2 device and other function blocks. The following table lists the source devices for each clock.
| Ref. Des. | Feature | Notes |
|---|---|---|
| U6 |
AMD
Spartan
UltraScale+ FPGA 100 MHz, 1.8 V, LVDS |
Transko TLSM2-L50CQ18ST1-100.000M-TR |
| U2 | HyperRAM 64 Mb memory 200 MHz, 1.8 V, LVDS |
AMD Spartan UltraScale+ FPGA |
| U85 | QSPI Flash 128 Mb memory 100 MHz, LVCMOS |
EMCCLK |
| U31 | Ethernet PHY 25 MHz xtal |
Epson FA-238_25.0000MB-C3 |
| U11 | USB UART/JTAG 12 MHz xtal |
ECS ECS-120-18-33-JGN-TR |
| U2 | HSIO Expansion 312/625 MHz, 1.8 V, LVDS |
AMD Spartan UltraScale+ FPGA |
The detailed device connections for the feature described in this section are documented in the board XDC file, referenced in Xilinx Design Constraints.