The evaluation board uses power management ICs (PMIC) and power regulators from Monolithic Power Systems to supply the core and auxiliary voltages listed in the following tables. The detailed device connections for the feature described in this section are documented in the SCU35 board schematic.
| Rail Name | Nominal Voltage (V) | Max Current (A) | Device | INA700 Addr |
|---|---|---|---|---|
| VR_OUT_20V | 9-20 | 3 | TI TPS25730D | NA |
| VR_EXT_5V0 | 5.0 | 13 | MP2422 | NA |
| VR_INT_5V0 | 5.0 | 13 | MP2422 |
0x44
I2C1 |
| VR_UTIL_3V3 | 3.3 | 5 | MP8770CGQ | NA |
| VR_VCCINT_0V85 | 0.85 | 5 | MP8770CGQ |
0x45
I2C1 |
| VR_VCCINT_IO_BRAM_0V85 | 0.85 | 1 | MP2183C | NA |
| VR_VCCADC_1V8 | 1.8 | 0.5 | MP2181 | NA |
| VR_VCCAUX_HDIO_1V8 | 1.8 | 1 | MP2183C | NA |
| VR_VCCAUX_HPIO_1V8 | 1.8 | 0.5 | MP2181 | NA |
| VR_VCCO_0_1V8 | 1.8 | 0.5 | MP2181 | NA |
| VR_VCCO_45_46_ADJ | 1.2, 1.5, 1.8, 2.5, 3.3 (deafult) | 5 | MP8770CGQ | NA |
| VR_VCCO_47_1V8 | 1.8 | 4 | MP8770CGQ | NA |
| VR_VCCO_65_66_67_68_3V3 | 3.3 | 5 | MP8770CGQ | NA |
Note: Bus short names are decoded
as:
I2C1 = I2C1_INA_SCL/SDA
See I2C Buses and Connections for I2C diagrams and more details.
The PCB layout and power system design meet the recommended criteria described in the UltraScale Architecture PCB Design User Guide (UG583).
More information about the power system regulator components can be found at the Monolithic Power Systems (MPS) website.
Important: This power delivery
solution is not recommended to be copied into your system as-is. Power subsystems
for evaluation boars are over designed for silicon evaluation. For more information
and guidelines for an optimal solution, see Answer Record 000037816.