The VEK385 evaluation board uses power management ICs (PMIC) and power regulators from MPS to supply the core and auxiliary voltages listed in the following tables. The detailed device connections for the feature described in this section are documented in the VEK385 board schematic.
| Domain | Rail Name | Nominal Voltage (V) | Max Current (A) | PMBUS Addr | PMIC Port | INA7xx Addr | Voltage Monitor Addr | Voltage Monitor Port |
|---|---|---|---|---|---|---|---|---|
| FPD | VCC_FPD | 0.88 | 24 | PMBUS1 0x23
|
8 | PMBUS1_INA0x40
|
PMBUS1
|
VIN2 |
| FPD | VCC_USB2_504 | 0.80 | 0.10 | PMBUS1 0x12
|
N/A | N/A | N/A | N/A |
| FPD | VCC_PAUX_504 | 0.80 | 0.10 | PMBUS2 0x13
|
N/A | N/A | N/A | N/A |
| FPD | VCC_USB3_504 | 0.80 | 0.20 | PMBUS2 0x14
|
N/A | N/A | N/A | N/A |
| FPD | VCCIO_USB2_504 | 3.30 | 0.20 | PMBUS2 0x15
|
N/A | N/A | N/A | N/A |
| FPD | VCCREG_USB2_504 | 3.30 | 0.20 | PMBUS2 0x16
|
N/A | N/A | N/A | N/A |
| FPD | VCCIO_PAUX_504 | 1.80 | 0.10 | PMBUS2
|
N/A | N/A | N/A | N/A |
| FPD | VCCIO_USB3_504 | 1.20 | 0.50 | PMBUS2 0x18
|
N/A | N/A | N/A | N/A |
| LPD | VCC_LPD | 0.88 | 6 | PMBUS1 0x23
|
9 | PMBUS1_INA 0x44
|
PMBUS1
|
VIN3 |
| LPD | VCCAUX_LPD | 1.50 | 2 | PMBUS2 0x19
|
N/A | PMBUS1_INA 0x45
|
PMBUS1
|
VIN4 |
| LPD | VCCO_50X | 1.80 | 3 | PMBUS1 0x1A
|
N/A | PMBUS1_INA 0x46
|
PMBUS1
|
VIN5 |
| LPD | VCC_MIPI_507 | 0.80 | 0.50 | PMBUS2 0x1E
|
N/A | PMBUS1_INA 0x47
|
N/A | N/A |
| LPD | VCCIO_MIPI_507 | 1.20 | 0.50 | PMBUS2 0x1F
|
N/A | PMBUS2_INA 0x44
|
N/A | N/A |
| SoC | VCC_SOC_IO | 0.80 | 30 | PMBUS1 0x22
|
1-2 | PMBUS1_INA 0x41
|
PMBUS1
|
VIN1PN |
| SoC | VCCAUX | 1.50 | 5 | PMBUS2 0x01
|
N/A | PMBUS2_INA 0x46
|
PMBUS1
|
VIN3 |
| SoC | VCC_MMD | 0.80 | 6 | PMBUS1 0x22
|
9 | PMBUS4_INA 0x44
|
PMBUS1
|
VIN5 |
| SoC | VCCO_7xx_LP5 | 1.00 | 10 | PMBUS1 0x22
|
8 | PMBUS3_INA 0x47
|
PMBUS1
|
VIN4 |
| SoC | VADJ_FMC | 1.20 | 6 | PMBUS2 0x02
|
N/A | PMBUS2_INA 0x47
|
N/A | N/A |
| PL | VCCINT | 0.80 | 90 | PMBUS1 0x23
|
1-4 | PMBUS1_INA 0x48,
0x49, 0x4A, 0x4B
|
PMBUS1
|
VIN1PN |
| PL | VCC_RAM | 0.80 | 2 | PMBUS1 0x24
|
9 | PMBUS4_INA 0x45
|
PMBUS1 0x07
|
VIN6 |
| PL | VCCO_40X | 3.30 | 2 | PMBUS2 0x1B
|
N/A | PMBUS3_INA 0x44
|
N/A | N/A |
| PL | GTYP_AVCC | 0.92 | 4 | PMBUS1 0x24
|
8 | PMBUS4_INA 0x46
|
PMBUS1 0x07
|
VIN3 |
| PL | GTYP_AVCCAUX | 1.50 | 0.50 | PMBUS1 0x1C
|
N/A | PMBUS3_INA 0x45
|
PMBUS1 0x07
|
VIN4 |
| PL | GTYP_AVTT | 1.20 | 4 | PMBUS1 0x1D
|
N/A | PMBUS3_INA 0x46
|
PMBUS1 0x07
|
VIN5 |
| AIE | VCC_AIE | 0.80 | 90 | PMBUS1 0x24
|
1-4 |
PMBUS2_INA
|
PMBUS1 0x06
|
VIN1PN |
| UTIL0 | UTIL_5V0 | 5.00 | 20 | N/A | N/A | PMBUS2_INA 0x45
(Bank 504 only) |
PMBUS1 0x07
|
N/A |
| UTIL0 | UTIL_3V3 | 3.30 | 20 | N/A | N/A | N/A | N/A | N/A |
| UTIL1 | LP5_VDDH_1V05 | 1.05 | 5 | PMBUS2 0x03
|
N/A | N/A | N/A | N/A |
| UTIL1 | LP5_VDDQ_0V5 | 0.50 | 0.5 | PMBUS2 0x04
|
N/A | N/A | N/A | N/A |
| UTIL1 | UTIL_1V8 | 1.80 | 5 | N/A | N/A | N/A | N/A | N/A |
| UTIL1 | UTIL_2V5 | 2.50 | 5 | N/A | N/A | N/A | N/A | N/A |
| UTIL1 | UTIL_1V2 | 1.20 | 5 | N/A | N/A | N/A | N/A | N/A |
| UTIL1 | UTIL_ETH_VCC1V0 | 1.00 | 1 | N/A | N/A | N/A | N/A | N/A |
| SYSCTRL0 | SYS_VCC5V0 | 5.00 | 8 | N/A | N/A | N/A | N/A | N/A |
| SYSCTRL1 | SYS_VCC1V8 | 1.80 | 2 | N/A | N/A | N/A | N/A | N/A |
| SYSCTRL1 | SYS_VCC3V3 | 3.30 | 2 | N/A | N/A | N/A | N/A | N/A |
| SYSCTRL1 | SYS_VCC2V5 | 2.50 | 0.5 | N/A | N/A | N/A | N/A | N/A |
| SYSCTRL1 | SYS_ETH_VCC1V0 | 1.00 | 0.5 | N/A | N/A | N/A | N/A | N/A |
The FMCP HSPC (J13) VADJ pins are wired to the programmable rail VADJ_FMC. The VADJ_FMC rail is programmed to 1.20V by default, only 1.20V is supported. The VADJ_FMC rail also powers the 2VE3858 FMCP interface banks 705, 706, 707, 712, and 713. Documentation describing PMBus programming for the MPS power controllers is available on the MPS website. The PCB layout and power system design meet the recommended criteria described in the Versal Adaptive SoC PCB Design User Guide (UG863).
More information about the power system regulator components can be found at the MPS website.