Training Resources - 2025.1 English - UG1711

MicroBlaze V Processor Embedded Design User Guide (UG1711)

Document ID: UG1711
Release Date: 2025-05-29
Version: 2025.1 English

Introduction
Navigating Content by Design Process
Device Tools Flow Overview
General Steps for Creating an Embedded Processor Design
Embedded IP catalog
Making Manual Connections in a Design
Manually Creating and Connecting to I/O Ports
Platform Board Flow in IP Integrator
Memory-Mapping in the Address Editor
Running Design Rule Checks
Integrating a Block Design in the Top-Level Design
Generating Output Products
Creating an HDL Wrapper
Using the Vitis Software Platform
Exporting a Hardware Description
Using a MicroBlaze V Processor in an Embedded Design
Creating a MicroBlaze V Processor Design
Designing with the MicroBlaze V Processor
Converting from a Classic MicroBlaze Design
Using the MicroBlaze V Configuration Wizard
MicroBlaze V Configuration Wizard: Welcome Page
Select Processor Implementation
General Settings
MicroBlaze V Configuration Wizard: General Page
Instructions
Optimization
Fault Tolerance
MicroBlaze V Configuration Wizard: Cache Page
MicroBlaze V Configuration Wizard: Debug Page
Debug Options
MicroBlaze Debug Module Interface
Hardware Breakpoints
Performance Monitoring
Trace and Profiling
MicroBlaze V Configuration Wizard: Buses Page
Local Memory Bus Interfaces
AXI and ACE Interfaces
Stream Interfaces
Other Interfaces
MicroBlaze V Configuration Wizard: Advanced Mode
MicroBlaze V Advanced Mode Exception Tab
Bus Exceptions
Other Exceptions
MicroBlaze Advanced Mode Interrupt & Reset Tab
Interrupt
Vectors
Completing Connections
Block Automation
Using Connection Automation
Completing the Design
MicroBlaze V Processor Constraints
Taking the Design through Synthesis, Implementation, and Bitstream Generation
Exporting Hardware to the Vitis Integrated Design Environment
Multiple MicroBlaze Processor Designs
Instantiate MicroBlaze V IP Cores
Run Connection Automation
Re-Customizing AXI Interconnects
Mapping and Excluding Unwanted Slaves
Designing with the Memory IP Core
Adding the Memory IP
Making Connections with Block Automation
Adding a Clocking Wizard
Adding an AXI Master
Creating a Memory Map
Running Design Rule Checks
Implementing the Design
Reset and Clock Topologies in IP Integrator
MicroBlaze V Design without a Memory IP Core
MicroBlaze V Design with a Memory IP Core
Designs with Memory IP and the Clocking Wizard
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Training Resources
Revision History
Please Read: Important Legal Notices

Designing FPGAs Using the Vivado Design Suite 1 Training Course
Embedded Systems Design Training Course
Vivado Design Suite QuickTake Video Tutorials

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