Make the selections listed in the following table for each automation.
Connection | More Information | Setting |
---|---|---|
axi_gpio_0
|
The GPIO interface can be tied to several on-board interfaces. | Set the Selected Board Part Interface to led_8bits (LED). |
axi_gpio_0
|
The Master field is set to its default value of /microblaze_riscv_0 (Periph) . All other fields is set to its default value of Auto. |
Keep the default settings. |
axi_uartlite_0
|
The Master field is set to its default value of /microblaze_riscv_1 (Periph) . All other fields is set to its default value of Auto. |
Set the
Master field to /microblaze_riscv_1
(Periph) .
|
axi_uartlite_0
|
Set the Select Board Part Interface to the rs232_uart interface present on-board or tie it to a custom interface. | Keep the default setting of rs232_uart (UART) . |
axi_uartlite_1
|
The Master field is set to its default value of /microblaze_1 (Periph). All other fields is set to its default value of Auto. |
Keep the default settings. |
axi_uartlite_0
|
The Select Board Part Interface can be set to the rs232_uart interface present on-board or can be tied to a custom interface. | Because you already used the rs232_uart (UART) interface on the
board to connect to the /uartlite_0
instance, set the Select Board
Part Interface option to
Custom. |
clk_wiz_1
|
The input clock source of the Clocking Wizard can be tied to the several on-board clock sources or it can be tied to a Custom input clock. | Leave the Select Board Part Interface field to sys_diff_clock (System differential clock). |
clk_wiz_1
|
The reset pin of the Clocking Wizard can be tied to either the on-board reset source or to a custom input pin. | Leave the Select Board Part Interface to its default value of reset (FPGA Reset). |
microblaze_1_clk_wiz_1
|
The input clock source of the Clocking Wizard can be tied to the several on-board clock sources or it can be tied to a Custom input clock. | Set the Select Board Part Interface field to Custom. |
microblaze_1_clk_wiz_1
|
The reset pin of the Clocking Wizard can be tied to either the on-board reset source or to a custom input pin. | Leave the Select Board Part Interface to its
default value of reset (FPGA
Reset). |
rst_clk_wiz_1_100M
|
The reset pin of the Processor System Reset IP can be tied to either the on-board reset source or to a custom input pin. | Leave the Select Board Part Interface to its default value of reset (FPGA Reset). |
rst_microblaze_1_clk_wiz_1_100M
|
The reset pin of the Processor System Reset IP can be tied to either the on-board reset source or to a custom input pin. | Leave the Select Board Part Interface to its default value of reset (FPGA Reset). |
After running connection automation, one instance of the MicroBlaze V
(microblaze_0
) is connected to
two
slaves AXI Uartlite (axi_uartlite_0
) and AXI GPIO (axi_gpio_0
). The other instance of MicroBlaze V (microblaze_1
) is connected to the AXI Uartlite
(axi_uartlite_1
).