Other Interfaces - 2024.1 English

The MicroBlaze Trace interface can be used to view the processor software execution in simulation and in hardware. It is sufficient to enable the interface without actually connecting it, to get access to the signals in simulation, and to add them to an ILA in hardware.

The waveform can be related to the assembler and source code by looking at the executable object dump. In the Vitis software platform this can be viewed by double-clicking on the generated ELF file. It is also possible to generate an object dump from the ELF file with interspersed source code using the mb-objdump command. The Trace_PC and Trace_Instruction signals correspond to the address and instruction in the object dump. Note that these, and most other signals, are only valid when Trace_Valid_Instr is set.

Memory access addresses are shown using the Trace_Data_Address signal, which is valid when either Trace_Data_Read or Trace_Data_Write is set. Instruction results are written to a MicroBlaze destination register indicated by Trace_Reg_Addr when the Trace_Reg_Write signal is set, with the value shown by the Trace_New_Reg_Value signal.

The Trace_Exception_Kind signal, valid when Trace_Exception_Taken is set, indicates traps . This can be useful to find error conditions or interrupt related issues.

For a complete description of all the Trace bus interface signals, see section Trace Interface Description in MicroBlaze V Processor Reference Guide (UG1629) .

• When set to NONE, no lockstep interfaces are enabled.
• When set to LOCKSTEP_MASTER, it enables the Lockstep_Master_Out and Lockstep_Out output ports.
• When set to LOCKSTEP_SLAVE, it does the following:
  • Enables the Lockstep_Slave_In input port and Lockstep_Out output ports.
  • Sets the C_LOCKSTEP_SLAVE parameter to 1.

  The slave processor is visible as a CPU, and can have private LMB memory.

• LOCKSTEP_HIDDEN_SLAVE behaves the same way as LOCKSTEP_SLAVE, except that the slave processor is not visible as a CPU. This setting is recommended, except when using private LMB memory.

When this option is enabled, additional options become available under the Local Memory Bus Interfaces and AXI and ACE Interfaces section as shown in Other Interfaces. These options are explained below.

Figure 1. MicroBlaze V Configuration Wizard: Buses

• Use Monitor Interface for Local Memory Bus Instruction Interface: Select Monitor Interface for LMB instruction interface. This can be used to simplify connection of LMB for a lockstep slave processor when private LMB memory is not used.
• Use Monitor Interface for Local Memory Bus Data Interface: Select Monitor Interface for LMB data interface. This can be used to simplify connection of LMB for a lockstep slave processor when private LMB memory is not used.
• Use Monitor Interface for Peripheral AXI Instruction Interface: Select Monitor Interface for AXI peripheral data interface. This can be used to simplify connection of AXI for a lockstep slave processor.
• Use Monitor Interface for Peripheral AXI Data Interface: Select Monitor Interface for AXI peripheral data interface. This can be used to simplify connection of AXI for a lockstep slave processor.
• Use Monitor Interface for Cache AXI Instruction Interface: Select Monitor Interface for AXI cache instruction interface. This can be used to simplify connection of AXI for a lockstep slave processor.
• Use Monitor Interface for Cache AXI Data Interface: Select Monitor Interface for AXI cache data interface. This can be used to simplify connection of AXI for a lockstep slave processor.
• Temporal Depth: Allow configuration of temporal lockstep clock cycle delay of the slave processor.

There is also a monitor option for interrupt on the Interrupt & Reset tab:

Use Monitor Interface for Interrupt: Select Monitor Interface for the interrupt interface. This can be used to simplify connection of interrupt for a lockstep slave processor when a common interrupt source is used.