MicroBlaze V Design without a Memory IP Core - 2024.1 English

For any design that uses a MicroBlaze V processor without a Memory IP core, you can instantiate a Clocking Wizard IP to generate the clocks required. For the platform board flow, you can configure the connection as follows:

1. After instantiating a MicroBlaze V processor in the design, click Run Block Automation link. This creates the MicroBlaze V subsystem.
2. In the Run Block Automation dialog box, select the New Clocking Wizard option to instantiate the Clocking Wizard IP, and click OK.

   Running Block Automation also instantiates and connects the Proc Sys Reset IP to the various blocks in the design.

   The IP integrator canvas looks like the following figure.

   
3. Click Run Connection Automation and select /clk_wiz_1/CLK_IN1_D to connect the on-board clock to the input of the Clocking Wizard IP, according to the board definition.
   Note: You can customize the Clocking Wizard to generate the various clocks required by the design.
   
   
   
4. In the Run Connection Automation dialog box, select sys_diff_clock to select the board interface for the target board, or select Custom to tie a different input clock source to the Clocking Wizard IP, click OK.
   
   
5. For the reset pin of the Clocking Wizard, select the dedicated reset interface on the target board or a Custom reset input source.
   
   
   Note: Steps 4 and 5 above can also be done by dragging and dropping the System Differential Clock under the Clock Sources folder and FPGA Reset from the Reset folder in the Board tab.
6. For the ext_reset_in pin for the Processor System Reset block choose the same reset source as chosen for the Clocking Wizard in the step above or a Custom reset source.

   After you make your choice and click OK, the IP integrator canvas looks like the following figure.

   
   
   
   CAUTION:
   If the platform board flow is not used, ensure that the locked output of the Clocking Wizard is connected to the dcm_locked input of Proc_Sys_Reset.