MicroBlaze V Configuration Wizard: Cache Page - 2024.1 English

MicroBlaze V Processor Embedded Design User Guide (UG1711)

Document ID
UG1711
Release Date
2024-08-01
Version
2024.1 English

The following figure shows the Cache options page for the MicroBlaze V configuration.

Figure 1. MicroBlaze V Configuration Wizard: Cache Options
  • The Data Cache Features are:
    • Size in Bytes: Specifies the size of the data cache if C_USE_DCACHE is enabled. Not all architectures permit all sizes.
    • Line Length: Select between 4, 8, or 16 word cache line length for cache miss-transfers from external memory.
    • Base Address: Specifies the base address of the data cache. This parameter is used only if C_USE_DCACHE is enabled.
    • High Address: Specifies the high address of the data cache. This parameter is used only if C_USE_DCACHE is enabled.
    • Use Distributed RAM for Tags: Uses the data cache tags to hold the address and a valid bit for each cache line. When enabled, the data cache tags are stored in Distributed RAM instead of block RAM. This saves block RAM, and can increase the maximum frequency.
    • Enable Write-back Storage Policy: This parameter enables use of a write-back data storage policy. When this policy is in effect, the data cache only writes data to memory when necessary, which improves performance in most cases. With write-back enabled, data is stored by writing an entire cache line. Using write-back also requires that the cache is flushed by software when appropriate, to ensure that data is available in memory; for example, when using direct memory access (DMA). When not enabled, a write-through policy is used, which always writes data to memory immediately.