Instructions - 2024.2 English - UG1711

MicroBlaze V Processor Embedded Design User Guide (UG1711)
Document ID
UG1711
Release Date
2024-11-27
Version
2024.2 English
  • Enable Atomic Instructions: Enables atomic instructions according to the RISC-V "A" Standard Extension for Atomic Instructions.
  • Enable Integer Multiply and Divide: Enables hardware integer multiplication, division, and remainder instructions according to the RISC-V "M" Standard extension for Integer Multiplication and Division.
  • Enable Floating Point Unit: Enables a floating point unit (FPU) based on the IEEE-754 standard. Single-precision is available with the 32-bit processor implementation and 64-bit implementation. Using the FPU significantly improves the floating point performance of the application and significantly increases the size of MicroBlaze V.

    The FPU implements instructions according to the RISC-V 'F' and 'D' Standard Extensions for Floating Point.

    The compiler automatically uses the FPU instructions corresponding to setting of this parameter.

  • Enable Code Compression: Enable compressed instructions according to the RISC-V "C" Standard Extension for Compressed Instructions.
  • Enable Bit Manipulation Extension: Enable bit manipulation instructions according to RISC-V Bit-Manipulation extensions.
  • Privilege Mode: Set the available RISC-V privilege modes to Machine or User mode.
  • Select Extended Addressing: Set the memory addressing capability.
    • With the 32-bit processor implementation, this enables additional load/store instructions to be able to access a larger address space than 4 GB (32-bit address).
    • With the 64-bit processor implementation, the extended address is handled by normal load/store instructions. The data side LMB and AXI bus addresses are extended to the number of address bits corresponding to the selected memory size. The following are the available values:
      • NONE (32-bit address, no additional instructions)
      • 64GB (36-bit address)
      • 1TB (40-bit address)
      • 16TB (44-bit address)
      • 256TB (48-bit address)
      • 4PB (52 bit address)
      • 64PB (56-bit address)
      • 16EB (64-bit address)
  • Enable Additional Custom Instructions: Provides additional functionality when using AXI4-Stream links.

    The instructions are also extended with the following variants.

    • Atomic get, getd, put, and putd instructions
    • Test-only get and getd instructions
    • get and getd instructions that generate a stream exception if the control bit is not set
    Important: The extended stream instructions must be enabled to use these additional instructions, and at least one stream link must be selected. The stream exception must be enabled to use instructions that generate stream exceptions.