Once a design is implemented and the bitstream is generated, you can export the design to the Vitis software platform for software application development. If the processing logic(PL) does not contain any logic, you can export the design without implementing or generating the bitstream. Perform the following steps to export your design:
- Navigate to the Vivado File menu.
- Select .
The Export Hardware dialog box opens.
- Select the Include bitstream
option using the checkbox in the Platform
State page and click Next.
- In the Export Hardware
Platform window, click Next. Note: Do not change the auto-populated default value in the XSA file name.
- Click Finish. The exported hardware XSA file is generated in the project directory.
- After the hardware definition is exported, select to launch the Vitis software platform from Vivado.
- Click Open Workspace from the
Welcome to the Vitis Unified IDE
screen.
After you export the hardware definition to the Vitis software platform and launch, you can start writing your software application.
You can perform further debug and software download from the Vitis software platform.
Alternatively, you can import the ELF file for the software back into the Vivado tools, and integrate it with the FPGA bitstream for further download and testing.