Adding an AXI Master - 2024.1 English

MicroBlaze V Processor Embedded Design User Guide (UG1711)

Document ID
UG1711
Release Date
2024-08-01
Version
2024.1 English

To complete the Memory IP design, an AXI master such as a MicroBlaze V embedded processor, or an external processor is required. The following procedure lists the steps to instantiate a MicroBlaze V processor into the block design.

  1. Select the Add IP command, type Micro into the search field, and select the MicroBlaze V processor to add it to the design.
  2. Click Run Block Automation to construct a basic MicroBlaze V system, and configure the settings in the dialog box as follows:
    • Preset: None (or the one that is desired)
    • Local Memory: Selects the required amount of local memory from pull-down menu.
    • Local Memory ECC: Turns on ECC if desired.
    • Cache Configuration: Selects the required amount of Cache memory.
    • Debug Module: Specifies the type of debug module from the pull-down menu.
    • Peripheral AXI Interconnect: This option must be enabled.
    • Interrupt Controller: Optional.
    • Clock Connection: Selects the clock source from the pull-down menu.
  3. Click OK.

    The Run Block Automation adds and connects IP needed to support the MicroBlaze V processor into the block design. The block design should look similar to the following figure. The Memory IP core is not yet connected to the MicroBlaze V processor.



  4. At the top of the design canvas, click Run Connection Automation to connect the Memory IP core to the MicroBlaze V processor. The Run Connection Automation dialog box opens, as shown in the following figure.

  5. Select the S_AXI interface of the mig_7series_0.
    Note: For the UltraScale Memory IP, select the C0_DDR4_S_AXI interface of the mig_0.

    The /microblaze_0 (Cached) option should be selected by default.

  6. Select either the AXI Interconnect or the AXI SmartConnect for the Interconnect IP. For high bandwidth application (such as the Memory IP), the Auto option selects the AXI SmartConnect IP.
  7. Leave the rest of the options to their default values.
  8. Click OK.

This instantiates an AXI Interconnect and generates the required connection between the Memory IP core and the MicroBlaze processor.

Ensure to complete any remaining connections to the design, such as connecting to an external reset source or connecting any interrupt sources through a concat IP to the MicroBlaze V processor.