Adding a Clocking Wizard - 2024.1 English

MicroBlaze V Processor Embedded Design User Guide (UG1711)

Document ID
UG1711
Release Date
2024-08-01
Version
2024.1 English

A Clocking wizard IP is required in the block design to fulfill the clocking requirement in addition to the clock generated by the Memory IP core.

  1. Select the Add IP command, type Clock into the search field, and select the Clocking Wizard IP. The following figure shows a Clock Wizard IP with a Memory IP core within a design.

    Follow these steps to connect the Clocking Wizard to the Memory IP core:

  2. Connect the ui_clk or ui_addn_clk_0 output of the Memory IP and any other clocks generated to the clk_in1 input of the Clocking wizard, as shown in the following figure.
    Tip: Ensure to use the appropriate output clock pin with the desired frequency.
  3. For the UltraScale Memory IP, connect the c0_ddr4_ui_clk pin to the Clocking Wizard, as shown in the following figure.

  4. Connect the ui_clk_sync_rst pin of the Memory IP core to the reset pin of the Clocking wizard, as shown below.
  5. For the UltraScale Memory IP, connect the c0_ddr4_ui_clk_sync_rst pin to the Clocking wizard, shown in the following figure.

  6. Configure the Clocking wizard to generate any required clocks for the design, by double-clicking the IP.