-
Select Bus Interface: When this parameter
is set to AXI, AXI is selected for both peripheral and
cache access. When this parameter is set to ACE, AXI
is selected for peripheral access and ACE is selected for cache access, providing cache
coherency support. Note: To use ACE, do not set area optimization, write-back data cache, instruction cache streams, or victims cache data widths other than 32-bit. You must set Use Cache for All Memory Accesses for both caches.
-
Enable Peripheral AXI Interface Instruction
Interface: When this parameter is set, the peripheral AXI4-Lite
instruction interface is available. In many cases, this interface is not needed, in
particular if the Instruction Cache is enabled and
C_ICACHE_ALWAYS_USEDis set. - Enable Peripheral AXI Data Interface: When this parameter is set, the peripheral AXI data interface is available. This interface usually connects to peripheral I/O using AXI4-Lite, but it can be connected to memory also. If you enable exclusive access, the AXI4 protocol is used.