XPM_PMC_BRIDGE - XPM_PMC_BRIDGE - 2025.2 English - Parameterized Macro: AXI Memory Mapped (AXI Full) PMC BRIDGE - UG1704

Spartan UltraScale+ Libraries Guide (UG1704)
Document ID
UG1704
Release Date
2025-12-17
Version
2025.2 English

Parameterized Macro: AXI Memory Mapped (AXI Full) PMC BRIDGE

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_PMC_BRIDGE
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Introduction

This macro is used to instantiate AXI Memory Mapped (AXI Full) PMC Bridge in the Spartan UltraScale+ Devices.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
S_AXI_araddr Input ADDR_WIDTH S_AXI_clk NA Active ARADDR: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
S_AXI_arburst Input 1 S_AXI_clk NA Active ARBURST: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
S_AXI_arcache Input 1 S_AXI_clk NA Active ARCACHE: Indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.
S_AXI_arid Input ID_WIDTH S_AXI_clk NA Active ARID: The data stream identifier that indicates different streams of data.
S_AXI_arlen Input 1 S_AXI_clk NA Active ARLEN: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
S_AXI_arlock Input 1 S_AXI_clk NA Active ARLOCK: This signal provides additional information about the atomic characteristics of the transfer.
S_AXI_arprot Input 1 S_AXI_clk NA Active ARPROT: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
S_AXI_arqos Input 1 S_AXI_clk NA Active ARQOS: Quality of Service (QoS) sent on the write address channel for each write transaction.
S_AXI_arready Output 1 S_AXI_clk LEVEL_HIGH Active ARREADY: Indicates that the slave can accept a transfer in the current cycle.
S_AXI_arsize Input 1 S_AXI_clk NA Active ARSIZE: Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
S_AXI_arvalid Input 1 S_AXI_clk LEVEL_HIGH Active ARVALID: Indicates that the master is driving a valid transfer.
  • A transfer takes place when both ARVALID and ARREADY are asserted
S_AXI_awaddr Input ADDR_WIDTH S_AXI_clk NA Active AWADDR: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
S_AXI_awburst Input 1 S_AXI_clk LEVEL_HIGH Active AWBURST: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
S_AXI_awcache Input 1 S_AXI_clk LEVEL_HIGH Active AWCACHE: Indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.
S_AXI_awid Input ID_WIDTH S_AXI_clk NA Active AWID: Identification tag for the write address group of signals.
S_AXI_awlen Input 1 S_AXI_clk NA Active AWLEN: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
S_AXI_awlock Input 1 S_AXI_clk LEVEL_HIGH Active AWLOCK: This signal provides additional information about the atomic characteristics of the transfer.
S_AXI_awprot Input 1 S_AXI_clk LEVEL_HIGH Active AWPROT: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
S_AXI_awqos Input 1 S_AXI_clk LEVEL_HIGH Active AWQOS: Quality of Service (QoS) sent on the write address channel for each write transaction.
S_AXI_awready Output 1 S_AXI_clk LEVEL_HIGH Active AWREADY: Indicates that the slave can accept a transfer in the current cycle.
S_AXI_awsize Input 1 S_AXI_clk LEVEL_HIGH Active AWSIZE: Indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
S_AXI_awvalid Input 1 S_AXI_clk LEVEL_HIGH Active AWVALID: Indicates that the master is driving a valid transfer.
  • A transfer takes place when both AWVALID and AWREADY are asserted
S_AXI_bid Output ID_WIDTH S_AXI_clk NA Active BID: The data stream identifier that indicates different streams of data.
S_AXI_bready Input 1 S_AXI_clk LEVEL_HIGH Active BREADY: Indicates that the slave can accept a transfer in the current cycle.
S_AXI_bresp Output 1 S_AXI_clk NA Active BRESP: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
S_AXI_bvalid Output 1 S_AXI_clk LEVEL_HIGH Active BVALID: Indicates that the master is driving a valid transfer.
  • A transfer takes place when both BVALID and BREADY are asserted
S_AXI_clk Input 1 NA EDGE_RISING Active Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
S_AXI_rdata Output DATA_WIDTH S_AXI_clk NA Active RDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
S_AXI_rid Output ID_WIDTH S_AXI_clk NA Active RID: The data stream identifier that indicates different streams of data.
S_AXI_rlast Output 1 S_AXI_clk LEVEL_HIGH Active RLAST: Indicates the boundary of a packet.
S_AXI_rready Input 1 S_AXI_clk LEVEL_HIGH Active RREADY: Indicates that the slave can accept a transfer in the current cycle.
S_AXI_rresp Output 1 S_AXI_clk NA Active RRESP: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
S_AXI_rvalid Output 1 S_AXI_clk LEVEL_HIGH Active RVALID: Indicates that the master is driving a valid transfer.
  • A transfer takes place when both RVALID and RREADY are asserted
S_AXI_wdata Input DATA_WIDTH S_AXI_clk NA Active WDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
S_AXI_wlast Input 1 S_AXI_clk LEVEL_HIGH Active WLAST: Indicates the boundary of a packet.
S_AXI_wready Output 1 S_AXI_clk LEVEL_HIGH Active WREADY: Indicates that the slave can accept a transfer in the current cycle.
S_AXI_wstrb Input DATA_WIDTH / 8 S_AXI_clk NA Active WSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example:
  • STROBE[0] = 1b, DATA[7:0] is valid
  • STROBE[7] = 0b, DATA[63:56] is not valid
S_AXI_wvalid Input 1 S_AXI_clk LEVEL_HIGH Active WVALID: Indicates that the master is driving a valid transfer.
  • A transfer takes place when both WVALID and WREADY are asserted

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
ADDR_WIDTH DECIMAL 1 to 28 28 Defines the width of the ADDR ports, s_axi_araddr, s_axi_awaddr
DATA_WIDTH DECIMAL 8 to 32 32 Defines the width of the DATA ports, s_axi_rdata, s_axi_wdata
ID_WIDTH DECIMAL 1 to 8 1 Defines the width of the ID ports, s_axi_awid, s_axi_wid, s_axi_rid

VHDL Instantiation Template

Verilog Instantiation Template

Related Information