RAM64X8SW - RAM64X8SW - 2025.2 English - Primitive: 64-Deep by 8-bit Wide Random Access Memory with Single-Bit Write (Select RAM) - UG1704

Spartan UltraScale+ Libraries Guide (UG1704)
Document ID
UG1704
Release Date
2025-12-17
Version
2025.2 English

Primitive: 64-Deep by 8-bit Wide Random Access Memory with Single-Bit Write (Select RAM)

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM
Page-1 Graphic ID: SW & IP Sheet.2 RAM64X8SW RAM64X8SW Text Line.9 D D Text Line.14 WSEL[2:0] WSEL[2:0] Text Line.15 WE WE Text Line.46 WCLK WCLK Text Line.2 O[7:0] O[7:0] D Flip-Flop.1 Text Line.47 A[5:0] A[5:0] Sheet.10 X16623-033016 Sheet.11 Sheet.12 Sheet.13 X16623-061419

Introduction

The design element is a 64-bit deep by 8-bit wide random access memory with synchronous single-bit write, and asynchronous read capability. This RAM is implemented using LUT resources of the device (also known as Select RAM), and does not consume any of the Block RAM resources of the device. This component is implemented in a single CLB and consists of a 1-bit write, 8-bit read. The RAM64X8SW has WSEL for bit-selection, and an active-High write enable, WE, so that when the signal is High, and a rising edge occurs on the WCLK pin, a write is performed recording the value of the D input data pin into the selected bit element. The output O displays the contents of the 8-bit memory addressed by A, regardless of the WE value. When a write is performed, the output is updated to the new value shortly after the write completes.

Port Descriptions

Port Direction Width Function
A<5:0> Input 6 Read/Write Address Input.
D Input 1 Write Data.
O<7:0> Output 8 Read/Write port data output.
WCLK Input 1 Write Clock (reads are asynchronous).
WE Input 1 Write Enable.
WSEL<2:0> Input 3 Write Select (Single-Bit Select).

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT_A HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 7 of the RAM.
INIT_B HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 6 of the RAM.
INIT_C HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 5 of the RAM.
INIT_D HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 4 of the RAM.
INIT_E HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 3 of the RAM.
INIT_F HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 2 of the RAM.
INIT_G HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 1 of the RAM.
INIT_H HEX Any 64-bit HEX value All zeroes Specifies the initial contents of Bit 0 of the RAM.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Indicates whether the WCLK is active-High or active-Low.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM64X8SW: 64-Deep by 8-bit Wide Random Access Memory with Single-Bit Write (Select RAM)
--            Spartan UltraScale+
-- Xilinx HDL Language Template, version 2025.2

RAM64X8SW_inst : RAM64X8SW
generic map (
   INIT_A => X"0000000000000000", -- Initial contents of the RAM for Bit 7
   INIT_B => X"0000000000000000", -- Initial contents of the RAM for Bit 6
   INIT_C => X"0000000000000000", -- Initial contents of the RAM for Bit 5
   INIT_D => X"0000000000000000", -- Initial contents of the RAM for Bit 4
   INIT_E => X"0000000000000000", -- Initial contents of the RAM for Bit 3
   INIT_F => X"0000000000000000", -- Initial contents of the RAM for Bit 2
   INIT_G => X"0000000000000000", -- Initial contents of the RAM for Bit 1
   INIT_H => X"0000000000000000", -- Initial contents of the RAM for Bit 0
   IS_WCLK_INVERTED => '0'        -- Optional inversion for WCLK
)
port map (
   O => O,       -- 8-bit data output
   A => A,       -- 6-bit address input
   D => D,       -- 1-bit input: Write data input
   WCLK => WCLK, -- 1-bit input: Write clock input
   WE => WE,     -- 1-bit input: Write enable input
   WSEL => WSEL  -- 3-bit write select
);

-- End of RAM64X8SW_inst instantiation

Verilog Instantiation Template


// RAM64X8SW: 64-Deep by 8-bit Wide Random Access Memory with Single-Bit Write (Select RAM)
//            Spartan UltraScale+
// Xilinx HDL Language Template, version 2025.2

RAM64X8SW #(
   .INIT_A(64'h0000000000000000), // Initial contents of the RAM for Bit 7
   .INIT_B(64'h0000000000000000), // Initial contents of the RAM for Bit 6
   .INIT_C(64'h0000000000000000), // Initial contents of the RAM for Bit 5
   .INIT_D(64'h0000000000000000), // Initial contents of the RAM for Bit 4
   .INIT_E(64'h0000000000000000), // Initial contents of the RAM for Bit 3
   .INIT_F(64'h0000000000000000), // Initial contents of the RAM for Bit 2
   .INIT_G(64'h0000000000000000), // Initial contents of the RAM for Bit 1
   .INIT_H(64'h0000000000000000), // Initial contents of the RAM for Bit 0
   .IS_WCLK_INVERTED(1'b0)        // Optional inversion for WCLK
)
RAM64X8SW_inst (
   .O(O),       // 8-bit data output
   .A(A),       // 6-bit address input
   .D(D),       // 1-bit input: Write data input
   .WCLK(WCLK), // 1-bit input: Write clock input
   .WE(WE),     // 1-bit input: Write enable input
   .WSEL(WSEL)  // 3-bit write select
);

// End of RAM64X8SW_inst instantiation

Related Information

  • UltraScale Architecture Configurable Logic Block User Guide (UG574)