PLLE4_BASE - PLLE4_BASE - 2025.2 English - Primitive: Base Phase-Locked Loop (PLL) - UG1704

Spartan UltraScale+ Libraries Guide (UG1704)

Document ID
UG1704
Release Date
2025-12-17
Version
2025.2 English

Primitive: Base Phase-Locked Loop (PLL)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
Page-1 Sheet.1 PLLE4_BASE PLLE4_BASE Text Line.88 CLKOUT1B CLKOUT1B Text Line.93 CLKOUT1 CLKOUT1 Text Line.36 LOCKED LOCKED Text Line.39 PWRDWN PWRDWN Sheet.6 RST RST Text Line.6 CLKOUTPHYEN CLKOUTPHYEN Text Line.7 CLKIN CLKIN Text Line.8 CLKFBIN CLKFBIN Text Line.9 CLKOUT0 CLKOUT0 Text Line.10 CLKOUTPHY CLKOUTPHY Text Line.12 CLKFBOUT CLKFBOUT Text Line.11 CLKOUT0B CLKOUT0B D Flip-Flop.12 D Flip-Flop.23 Sheet.16 X15111-102615 Sheet.17 Sheet.18 Sheet.19 X15111-061319

Introduction

The PLLE4 is used for high-speed I/O clocking using Bitslice components as well as general clocking requirements. In general, the PLLE4 has less jitter and reduced power characteristics compared to the MMCME4 which makes it preferable for clocking behaviors that do not require features only available to the MMCME4.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog Yes