The PLLE4XP_BASE provide clocking to the PHY logic and I/Os. They can also be used as frequency synthesizers for a wide range of frequencies, serve as jitter filters, and provide basic phase shift capabilities and duty cycle programming The primary function of the XPLL is to support the clocking needs of Memory Interface IP and XP5IO Logic.
Port Descriptions
Port
Direction
Width
Function
Design Entry Method
Instantiation
No
Inference
No
IP and IP Integrator Catalog
Recommended
Available Attributes
Attribute
Type
Allowed Values
Default
Description
CLKFBOUT_MULT
DECIMAL
2 to 21
5
IS_CLKFBIN_INVERTED
BINARY
1'b0 to 1'b1
1'b0
Specifies whether or not to use the optional inversion on the
CLKFBIN pin.