Primitive: Input/Output Buffer DCI Enable
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Introduction
The primitive IOBUF_DCIEN_XP5 is only supported in XP5IO banks. It's function is the same as the IOBUF_DCIEN primitive supported in HP IO banks, except when the IBUFDISABLE pin is asserted, its output behaves differently than the IOBUF_DCIEN in HP banks. Please pay special attention in the design that uses both IOBUF_DCIEN and IOBUF_DCIEN_XP5.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| DCITERMDISABLE | Input | 1 | Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state. |
| I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
| IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic High. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
| IO | Inout | 1 | Bidirectional port to be connected directly to top-level inout port. |
| O | Output | 1 | Output path of the buffer. |
| T | Input | 1 | 3-state enable input signifying whether the buffer acts as an input or output. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| SIM_DEVICE | STRING | "ULTRASCALE", "ULTRASCALE_PLUS" | "ULTRASCALE_PLUS" | Set the device version for simulation functionality. |
| USE_IBUFDISABLE | STRING | "TRUE", "FALSE", "T_CONTROL" | "TRUE" | Set this attribute to "TRUE" to enable the IBUFDISABLE pin. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUF_DCIEN_XP5: Input/Output Buffer DCI Enable
-- Spartan UltraScale+
-- Xilinx HDL Language Template, version 2025.2
IOBUF_DCIEN_XP5_inst : IOBUF_DCIEN_XP5
generic map (
SIM_DEVICE => "ULTRASCALE", -- Set the device version for simulation functionality (ULTRASCALE)
USE_IBUFDISABLE => "TRUE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
O => O, -- 1-bit output: Buffer output
DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
I => I, -- 1-bit input: Buffer input
IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable
IO => IO, -- 1-bit inout: Buffer inout (connect directly to top-level port)
T => T -- 1-bit input: 3-state enable input
);
-- End of IOBUF_DCIEN_XP5_inst instantiation
Verilog Instantiation Template
// IOBUF_DCIEN_XP5: Input/Output Buffer DCI Enable
// Spartan UltraScale+
// Xilinx HDL Language Template, version 2025.2
IOBUF_DCIEN_XP5 #(
.SIM_DEVICE("ULTRASCALE"), // Set the device version for simulation functionality (ULTRASCALE)
.USE_IBUFDISABLE("TRUE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IOBUF_DCIEN_XP5_inst (
.O(O), // 1-bit output: Buffer output
.DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
.I(I), // 1-bit input: Buffer input
.IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable
.IO(IO), // 1-bit inout: Buffer inout (connect directly to top-level port)
.T(T) // 1-bit input: 3-state enable input
);
// End of IOBUF_DCIEN_XP5_inst instantiation