IOBUFE3_XP5 - IOBUFE3_XP5 - 2025.2 English - Primitive: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning - UG1704

Spartan UltraScale+ Libraries Guide (UG1704)

Document ID
UG1704
Release Date
2025-12-17
Version
2025.2 English

Primitive: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Page-1 Sheet.2 IOBUFE3 IOBUFE3_XP5 Sheet.3 T T Sheet.4 OSC_EN OSC_EN Sheet.5 OSC[3:0] OSC[3:0] Sheet.6 I I Buffer.30 Buffer.31 Sheet.9 O O Dynamic connector.33 Sheet.11 Sheet.12 VREF VREF Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 DCITERMDISABLE DCITERMDISABLE Sheet.18 IBUFDISABLE IBUFDISABLE Sheet.19 X00068-102425 X00068-102425

Introduction

The primitive IOBUFE3_XP5 is only supported in XP5IO banks. It's function is the same as the IOBUFE3 primitive supported in HP IO banks, except when the IBUFDISABLE pin is asserted, its output behaves differently than the IOBUFE3 in HP banks. Please pay special attention in the design that uses both IOBUFE3 and IOBUFE3_XP5.

Port Descriptions

Port Direction Width Function
DCITERMDISABLE Input 1 Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I Input 1 Input of OBUF. Connect to the logic driving the output port.
IBUFDISABLE Input 1 Disables input path through the buffer and forces to a logic High. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
IO Inout 1 Bidirectional port to be connected directly to top-level inout port.
O Output 1 Output path of the buffer.
OSC<3:0> Input 4 Offset cancellation value
OSC_EN Input 1 Offset cancellation enable
T Input 1 3-state enable input signifying whether the buffer acts as an input or output.
VREF Input 1 Vref input from HPIO_VREF

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_DEVICE STRING "ULTRASCALE", "ULTRASCALE_PLUS" "ULTRASCALE_PLUS" Set the device version for simulation functionality.
SIM_INPUT_BUFFER_OFFSET DECIMAL -50 to 50 0 Offset value for simulation purposes.
USE_IBUFDISABLE STRING "FALSE", "T_CONTROL", "TRUE" "FALSE" Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

Related Information

  • Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
  • Vivado Design Suite Properties Reference Guide (UG912)